Placement, modules, components and accessories; the ones that exist and the the nice-to-be's
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raph38130
- Posts: 4
- Joined: Tue Jul 07, 2015 7:30 am
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by raph38130 » Wed Jul 08, 2015 12:09 pm
Hi team
this is my first attempt at re synthesising rp from scratch (so I cant say if it is specific to this version of xilinx vivado)
there is an issue with I/O configuration
Code: Select all
INFO: [DRC 23-27] Running DRC with 8 threads
ERROR: [DRC 23-20] Rule violation (IOSTDTYPE-1) IOStandard Type - I/O port vinn_i[0] is Single-Ended but has an IOStandard of TMDS_33 which can only support Differential
from 0 to 4, and same vinp_i
any suggestions ?
thanks
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Nils Roos
- Posts: 1441
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- Location: Königswinter
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by Nils Roos » Wed Jul 08, 2015 12:51 pm
This is an issue for all versions of Vivado from 2014.1 onward. 2013.3 needs these IOSTANDARDS to be set to TMDS_33, whereas 2014.1 and later need them to be LVCMOS33.
You can change them in the file FPGA/release1/fpga/code/red_pitaya.xdc like this:
Code: Select all
set_property IOSTANDARD LVCMOS33 [get_ports {vinp_i[*]}]
set_property IOSTANDARD LVCMOS33 [get_ports {vinn_i[*]}]
You will probably run into timing violations later, too. See
this post for a solution.
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raph38130
- Posts: 4
- Joined: Tue Jul 07, 2015 7:30 am
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by raph38130 » Thu Jul 09, 2015 3:52 pm
okay that is okay now
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