vivado 2015.2 issue

[raph38130]

Hi team

this is my first attempt at re synthesising rp from scratch (so I cant say if it is specific to this version of xilinx vivado)

there is an issue with I/O configuration

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INFO: [DRC 23-27] Running DRC with 8 threads
ERROR: [DRC 23-20] Rule violation (IOSTDTYPE-1) IOStandard Type - I/O port vinn_i[0] is Single-Ended but has an IOStandard of TMDS_33 which can only support Differential

from 0 to 4, and same vinp_i

any suggestions ?
thanks

[Nils Roos]

This is an issue for all versions of Vivado from 2014.1 onward. 2013.3 needs these IOSTANDARDS to be set to TMDS_33, whereas 2014.1 and later need them to be LVCMOS33.

You can change them in the file FPGA/release1/fpga/code/red_pitaya.xdc like this:

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set_property IOSTANDARD LVCMOS33 [get_ports {vinp_i[*]}]
set_property IOSTANDARD LVCMOS33 [get_ports {vinn_i[*]}]

You will probably run into timing violations later, too. See this post for a solution.

[raph38130]

okay that is okay now