until now I have not installed the Xilinx-Tools, can anybody tell me about the percentage of the
used LUTs/registers/PLLs for the current FPGA solution? Is there some more space for me?
Cheers
Uli, DF4IAH
Percentage of used LUTs/registers of current FPGA solution?
-
DF4IAH
- Posts: 14
- Joined: Thu Aug 20, 2015 12:19 am
- Location: JN49HL / Germany nr. Heidelberg
Percentage of used LUTs/registers of current FPGA solution?
Hi,
until now I have not installed the Xilinx-Tools, can anybody tell me about the percentage of the
used LUTs/registers/PLLs for the current FPGA solution? Is there some more space for me?
Cheers
Uli, DF4IAH
until now I have not installed the Xilinx-Tools, can anybody tell me about the percentage of the
used LUTs/registers/PLLs for the current FPGA solution? Is there some more space for me?
Cheers
Uli, DF4IAH
-
Nils Roos
- Posts: 1441
- Joined: Sat Jun 07, 2014 12:49 pm
- Location: Königswinter
Re: Percentage of used LUTs/registers of current FPGA soluti
Summary generated from the current master branch:
FF: 15%
LUT: 28%
Memory LUT: 3%
BRAM: 50%
DSP: 35%
PLL: 50%
You should be able to find some space for your own experiments in there.
Here's the detailed utilization report:
FF: 15%
LUT: 28%
Memory LUT: 3%
BRAM: 50%
DSP: 35%
PLL: 50%
You should be able to find some space for your own experiments in there.
Here's the detailed utilization report:
Code: Select all
Utilization Design Information
Table of Contents
-----------------
1. Slice Logic
2. Slice Logic Distribution
3. Memory
4. DSP
5. IO and GTX Specific
6. Clocking
7. Specific Feature
8. Primitives
9. Black Boxes
10. Instantiated Netlists
1. Slice Logic
--------------
+----------------------------+------+-------+-----------+-------+
| Site Type | Used | Loced | Available | Util% |
+----------------------------+------+-------+-----------+-------+
| Slice LUTs | 4973 | 0 | 17600 | 28.25 |
| LUT as Logic | 4802 | 0 | 17600 | 27.28 |
| LUT as Memory | 171 | 0 | 6000 | 2.85 |
| LUT as Distributed RAM | 160 | 0 | | |
| LUT as Shift Register | 11 | 0 | | |
| Slice Registers | 5381 | 0 | 35200 | 15.28 |
| Register as Flip Flop | 5364 | 0 | 35200 | 15.23 |
| Register as Latch | 17 | 0 | 35200 | 0.04 |
| F7 Muxes | 13 | 0 | 8800 | 0.14 |
| F8 Muxes | 1 | 0 | 4400 | 0.02 |
+----------------------------+------+-------+-----------+-------+
2. Slice Logic Distribution
---------------------------
+-------------------------------------------------------------+-----------+-------+-----------+-------+
| Site Type | Used | Loced | Available | Util% |
+-------------------------------------------------------------+-----------+-------+-----------+-------+
| Slice | 1948 | 0 | 4400 | 44.27 |
| LUT as Logic | 4802 | 0 | 17600 | 27.28 |
| using O5 output only | 1 | | | |
| using O6 output only | 3925 | | | |
| using O5 and O6 | 876 | | | |
| LUT as Memory | 171 | 0 | 6000 | 2.85 |
| LUT as Distributed RAM | 160 | 0 | | |
| using O5 output only | 0 | | | |
| using O6 output only | 0 | | | |
| using O5 and O6 | 160 | | | |
| LUT as Shift Register | 11 | 0 | | |
| using O5 output only | 2 | | | |
| using O6 output only | 3 | | | |
| using O5 and O6 | 6 | | | |
| LUT Flip Flop Pairs | 6193 | 0 | 17600 | 35.18 |
| fully used LUT-FF pairs | 3312 | | | |
| LUT-FF pairs with unused LUT | 1223 | | | |
| LUT-FF pairs with unused Flip Flop | 1658 | | | |
| Unique Control Sets | 205 | | | |
| Minimum number of registers lost to control set restriction | 507(Lost) | | | |
+-------------------------------------------------------------+-----------+-------+-----------+-------+
3. Memory
---------
+-------------------+------+-------+-----------+-------+
| Site Type | Used | Loced | Available | Util% |
+-------------------+------+-------+-----------+-------+
| Block RAM Tile | 30 | 0 | 60 | 50.00 |
| RAMB36/FIFO* | 30 | 0 | 60 | 50.00 |
| RAMB36E1 only | 30 | | | |
| RAMB18 | 0 | 0 | 120 | 0.00 |
+-------------------+------+-------+-----------+-------+
* Note: Each Block RAM Tile only has one FIFO logic available and therefore can accommodate only one FIFO36E1 or one FIFO18E1. However, if a FIFO18E1 occupies a Block RAM Tile, that tile can still accommodate a RAMB18E1
4. DSP
------
+----------------+------+-------+-----------+-------+
| Site Type | Used | Loced | Available | Util% |
+----------------+------+-------+-----------+-------+
| DSPs | 28 | 0 | 80 | 35.00 |
| DSP48E1 only | 28 | | | |
+----------------+------+-------+-----------+-------+
5. IO and GTX Specific
----------------------
+-----------------------------+------+-------+-----------+--------+
| Site Type | Used | Loced | Available | Util% |
+-----------------------------+------+-------+-----------+--------+
| Bonded IOB | 95 | 95 | 100 | 95.00 |
| IOB Master Pads | 45 | | | |
| IOB Slave Pads | 46 | | | |
| IOB Flip Flops | 32 | 32 | | |
| Bonded IPADs | 2 | 2 | 2 | 100.00 |
| Bonded IOPADs | 0 | 0 | 130 | 0.00 |
| IBUFGDS | 0 | 0 | 96 | 0.00 |
| IDELAYCTRL | 0 | 0 | 2 | 0.00 |
| IN_FIFO | 0 | 0 | 8 | 0.00 |
| OUT_FIFO | 0 | 0 | 8 | 0.00 |
| PHASER_REF | 0 | 0 | 2 | 0.00 |
| PHY_CONTROL | 0 | 0 | 2 | 0.00 |
| PHASER_OUT/PHASER_OUT_PHY | 0 | 0 | 8 | 0.00 |
| PHASER_IN/PHASER_IN_PHY | 0 | 0 | 8 | 0.00 |
| IDELAYE2/IDELAYE2_FINEDELAY | 0 | 0 | 100 | 0.00 |
| ODELAYE2/ODELAYE2_FINEDELAY | 0 | 0 | 0 | 0.00 |
| IBUFDS_GTE2 | 0 | 0 | 0 | 0.00 |
| ILOGIC | 29 | 29 | 100 | 29.00 |
| IFF_Register | 28 | 28 | | |
| ISERDES | 1 | 1 | | |
| OLOGIC | 24 | 24 | 100 | 24.00 |
| OUTFF_Register | 4 | 4 | | |
| OUTFF_ODDR_Register | 19 | 19 | | |
| OSERDES | 1 | 1 | | |
+-----------------------------+------+-------+-----------+--------+
6. Clocking
-----------
+--------------+------+-------+-----------+-------+
| Site Type | Used | Loced | Available | Util% |
+--------------+------+-------+-----------+-------+
| BUFGCTRL | 8 | 0 | 32 | 25.00 |
| BUFIO | 1 | 1 | 8 | 12.50 |
| BUFIO only | 1 | 1 | | |
| MMCME2_ADV | 0 | 0 | 2 | 0.00 |
| PLLE2_ADV | 1 | 0 | 2 | 50.00 |
| BUFMRCE | 0 | 0 | 4 | 0.00 |
| BUFHCE | 0 | 0 | 48 | 0.00 |
| BUFR | 1 | 0 | 8 | 12.50 |
+--------------+------+-------+-----------+-------+
7. Specific Feature
-------------------
+-------------+------+-------+-----------+--------+
| Site Type | Used | Loced | Available | Util% |
+-------------+------+-------+-----------+--------+
| BSCANE2 | 0 | 0 | 4 | 0.00 |
| CAPTUREE2 | 0 | 0 | 1 | 0.00 |
| DNA_PORT | 1 | 1 | 1 | 100.00 |
| EFUSE_USR | 0 | 0 | 1 | 0.00 |
| FRAME_ECCE2 | 0 | 0 | 1 | 0.00 |
| ICAPE2 | 0 | 0 | 2 | 0.00 |
| STARTUPE2 | 0 | 0 | 1 | 0.00 |
| XADC | 1 | 1 | 1 | 100.00 |
+-------------+------+-------+-----------+--------+
8. Primitives
-------------
+-------------+------+
| Ref Name | Used |
+-------------+------+
| FDRE | 5193 |
| LUT6 | 1571 |
| LUT4 | 1283 |
| LUT2 | 1084 |
| LUT5 | 800 |
| LUT3 | 585 |
| CARRY4 | 488 |
| LUT1 | 355 |
| RAMD32 | 240 |
| FDSE | 180 |
| BIBUF | 130 |
| RAMS32 | 80 |
| IBUF | 54 |
| OBUF | 33 |
| RAMB36E1 | 30 |
| ZHOLD_DELAY | 28 |
| DSP48E1 | 28 |
| FDCE | 23 |
| ODDR | 19 |
| SRL16E | 17 |
| LDCE | 17 |
| OBUFT | 16 |
| MUXF7 | 13 |
| BUFG | 8 |
| OBUFDS | 4 |
| IBUFDS | 3 |
| INV | 2 |
| XADC | 1 |
| PS7 | 1 |
| PLLE2_ADV | 1 |
| OSERDESE2 | 1 |
| MUXF8 | 1 |
| ISERDESE2 | 1 |
| DNA_PORT | 1 |
| BUFR | 1 |
| BUFIO | 1 |
+-------------+------+
9. Black Boxes
--------------
+----------+------+
| Ref Name | Used |
+----------+------+
10. Instantiated Netlists
-------------------------
+----------+------+
| Ref Name | Used |
+----------+------+
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