Protection of GPIO pins

[martijnj]

This may be a stupid question, but I want to connect a TTL (0-5V) signal to the external trigger (DIO0_P). I am concerned by the following statement in the Hardware Specs (footnote N):

To avoid speed limitations on digital General Purpose Input/Output pins are directly connected to FPGA. FPGA decoupling and pin protection is to be addressed within extension module designs. User is responsible for pin handling.

I assume some kind of optocoupler or level shifter using the 3.3V supply on e.g. E1 pin 1 could be used. Any recommendations for what to use? I'm only concerned about inputs so unidirectional is fine. I don't want to introduce significantly delay since I'm acquiring at 125MS/s though some delay is obviously unavoidable.

Or is the FPGA 5V tolerant and the above is a blanket statement? I couldn't find any information on this when I looked.

Thanks in advance for your help!

[Nils Roos]

Information about the physical capabilities of the GPIO can be found in "Zynq-7000 All Programmable SoC (Z-7010, Z-7015, and Z-7020): DC and AC Switching Characteristics" (Xilinx document id DS187).

My interpretation of the information contained therein is that the ZYNQ SoC is not 5V tolerant. Absolute maximum ratings for PL IO pins are listed as Vcco + 0.55V with Vcco <= 3.6V . The recommended operating conditions are a bit lower.

You should at least use a logic level shifter. Most manufacturers and resellers have parametric search functions nowadays, so you should have no trouble finding a device that matches your requirements.