Configuration Device

[sdon]

Hi, I am using the Red Pitaya as a development board.

Thus far I have used a JTAG interface to download my compiled FPGA code using Vivado. I am currently not using the microprocessor part of the SoC.

I would like to keep the hardware programmed into the FPGA when it is power cycled. Is there a configuration device on the board that I can use to do this? Otherwise can I do this using memory in the microprocessor? Could you give me some tips on how to go about doing this please?

Thanks,
Sean

[Nils Roos]

Hi Sean,

the only permanent storage of sufficient size available on the Red Pitaya is the sd card. The ZYNQ is configured to search a bootable medium there on power-up.

The way to go is to package your bitstream with a first stage boot loader (fsbl) into a "boot.bin" file and put it on the card. Xilinx supplies a default fsbl that initializes the on-chip peripherals and then searches for an embedded bitstream and programs it into the PL. You should be able to use that with a few minor modifications - like putting core0 to sleep instead of searching and loading a second stage bootloader.

See the ZYNQ technical reference manual, chapter 6 and the software developers guide, chapter 3 for more details.

[sdon]

Hi Nils,

Thanks for this. Just to confirm there are no jumpers on the board to switch between JTAG/SD card boot? I have at no point specified any processor or SD card pins. I only have a Vivado project in which the pins to the GPIO/ADC/DACs/LEDs are specified.

I have tried using the default FSBL project in SDK. (Hardware Platform: ZC702_hw_platform, Processor: ps7_cortexa9_0)

Using the "Create Zynq Boot Image" tool in SDK I have put the bootloader file (.elf) and my bitstream file that I also use for JTAG (.bit) and created a BOOT.bin file.

I save "BOOT.bin" to a 32Gb microSD card, put it into the RedPitaya and power up. ....no luck.

With the SD card inserted I can still program the FPGA using the JTAG interface and its functionality is correct.

I have also tried to add the default "hello world" program in SDK to the BSK - it compiles fine but I don't see the FPGA functionality after power up. I have also tried setting the "NON_PS_INSTANTIATED_BITSREAM" compilation flag in the FSBL project but still don't see FPGA function.

It is likely I am missing something general rather than specific to the Red Pitaya but I thought I should check!

Thanks again,
Sean

[Nils Roos]

I have tried using the default FSBL project in SDK. (Hardware Platform: ZC702_hw_platform, Processor: ps7_cortexa9_0)

Using the "Create Zynq Boot Image" tool in SDK I have put the bootloader file (.elf) and my bitstream file that I also use for JTAG (.bit) and created a BOOT.bin file.

I don't have any experience with putting together the FSBL through the SDK. I always used the Red Pitaya components with modifications as neccessary.

I save "BOOT.bin" to a 32Gb microSD card, put it into the RedPitaya and power up. ....no luck.

Just to check: is your sd-card's primary partition formatted as FAT32 ? Also, try "boot.bin" (lowercase) - not sure if it matters, though.

Just to confirm there are no jumpers on the board to switch between JTAG/SD card boot?

As far as I know the configuration pins have weak pull-ups / pull-downs soldered on the board. There are no jumpers to change the configuration.

I have at no point specified any processor or SD card pins. I only have a Vivado project in which the pins to the GPIO/ADC/DACs/LEDs are specified.

When developing FPGA designs for the Red Pitaya, you should at least use the full original pinout constraints and incorporate a block design with the ZYNQ - again, configured as in the original - in it. That last bit is particular important for booting from sd-card. You'll probably also need to connect all the FIXED_IO_... interfaces as in red_pitaya_top.v in your top-level Verilog code; if you want to access external RAM, you should also provide connections to the DDR... interface.

(Note: I am not yet familiar with the new ecosystem build process, so I describe the 'old' way and the links point to 0.93)