Background spectrum with Red Pitaya

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lilltroll
Posts: 3
Joined: Sat Jan 31, 2015 11:47 am

Background spectrum with Red Pitaya

Post by lilltroll » Sat Jan 31, 2015 12:13 pm

Hi

I'm interested in buying a Red Pitaya, but I would like to know more about the background noise in the device before I buy.
Is their any performance plots to view anywhere? (Not just the numbers)

If not:
Could anyone run a sine wave at f = fs/128 at -1 dBFS on the DAC, and connect a cable from the output to the input and run a FFT with rectangular Window of a length of at least 262144 samples and post the result on the forum? (If the DAC and ADC is running on the same Materclock, their shouldn't be any sidebands in the measurement). If mean value spectra is implemented in the software, it would be interesting to also see a plot of the mean value spectra over ~500 blocks.

Also just running the ADC without the DAC with a grounded or 50 Ohm terminated input and performing the same spectrum measurement.

pavel-demin
Posts: 33
Joined: Tue Dec 23, 2014 10:52 pm

Re: Background spectrum with Red Pitaya

Post by pavel-demin » Mon Feb 02, 2015 12:08 pm

Hi,

I've just generated a sine wave using Xilinx DDS IP core with the following parameters:
DDS_CLOCK_RATE 125
SPURIOUS_FREE_DYNAMIC_RANGE 84
FREQUENCY_RESOLUTION 0.5
AMPLITUDE_MODE Unit_Circle
OUTPUT_SELECTION Sine
OUTPUT_FREQUENCY1 0.9765625

I'd say that the resulting sine wave should correspond more or less (f = fs/128 at -6 dBFS) to what you requested.

Here is a link to a file with 1M samples:

https://googledrive.com/host/0B-t5klOOy ... ac-adc.txt

Please, share your spectrum plot.

Cheers,

Pavel
Last edited by pavel-demin on Mon Feb 02, 2015 5:47 pm, edited 2 times in total.

pavel-demin
Posts: 33
Joined: Tue Dec 23, 2014 10:52 pm

Re: Background spectrum with Red Pitaya

Post by pavel-demin » Mon Feb 02, 2015 1:34 pm

I've just managed to draw a spectrum plot using R.

Here is the plot:
Image

and here is the code in R:

Code: Select all

DATA <- matrix(scan("red-pitaya-sine-dac-adc.txt", n = 1048576), 1, 1048576, byrow = TRUE)[1,]

# FFT size = number of COMPLEX sinusoids
N <- 1048576
# sampling rate in MHz (arbitrary)
fs <- 125

H <- fft((DATA-mean(DATA))/8192)

nnfi <- 1:(N/2+1)     # non-negative-frequency indices
Hnnf <- H[nnfi]       # lose negative-frequency samples
nnfb <- nnfi-1        # corresponding bin numbers
f <- nnfb*fs/N        # frequency axis in MHz
gains <- Mod(Hnnf)    # amplitude response

y <- 20*log10(gains*2/N)
x <- f
png("red-pitaya-sine-dac-adc-fft.png") 
matplot(x, y, type = "l", ylim=c(-150,0),
  main = expression(paste("Red Pitaya FFT")),
  ylab = expression(paste("Magnitude in dB")),
  xlab = expression(paste("Frequency in MHz")))
grid(col = "black")
dev.off()
Last edited by pavel-demin on Mon Feb 02, 2015 7:40 pm, edited 1 time in total.

pavel-demin
Posts: 33
Joined: Tue Dec 23, 2014 10:52 pm

Re: Background spectrum with Red Pitaya

Post by pavel-demin » Mon Feb 02, 2015 5:56 pm

Just noticed that negative amplitudes were clipped in my initial sample. I've regenerated a sample at -6dBFS and updated my previous comments.

lilltroll
Posts: 3
Joined: Sat Jan 31, 2015 11:47 am

Re: Background spectrum with Red Pitaya

Post by lilltroll » Mon Feb 02, 2015 7:25 pm

THANKS!

So the current web-based tools only supports 16 ksample blocks, and to use larger chunks of data you need to implement something else yourself !?
Your code, is it streaming the data to DRAM in "realtime" , and later fetched by the ARM side ?
Is the 16k blocks a current limit in all existing APIs ?

Since the crystal on the board != 125 MHz, I assume a PLL is involved. Is the PPL and sampling frequency programmable?

Nils Roos
Posts: 1441
Joined: Sat Jun 07, 2014 12:49 pm
Location: Königswinter

Re: Background spectrum with Red Pitaya

Post by Nils Roos » Mon Feb 02, 2015 8:38 pm

The original scope has a 16kS buffer per channel. When that is full, acquisition stops and the data must be fetched by the CPU.
As long as an API uses the original scope fpga design, it can not record more than 16kS without interruption.

There are now at least two contributed solutions from users that circumvent the internal buffer and write the samples directly to external memory. This enables much longer recording without gaps in the data, but they are not integrated with the web-apps or cli tools (acquire, monitor, generate).
lilltroll wrote:Since the crystal on the board != 125 MHz, I assume a PLL is involved. Is the PPL and sampling frequency programmable?
The clock for the ADC and the whole sample processing path up to and including the DAC is generated by a 125MHz crystal oscillator. However, with some resoldering of a few jumpers and some changes in the fpga, the ADC clock can also be sourced by the ZYNQ.
crystal_osc.jpg
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