I want to try to read and write data to the addresses 0x40600000 to 0x406fffff, but I have not had much success. I tried creating a module specifically tailored to reading and writing data to that address space:
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module red_pitaya_free
(
// signals
input clk_i , //!< processing clock
input rstn_i , //!< processing reset - active low
// system bus
input sys_clk_i , //!< bus clock
input sys_rstn_i , //!< bus reset - active low
input [ 32-1: 0] sys_addr_i , //!< bus address
input [ 32-1: 0] sys_wdata_i , //!< bus write data
input [ 4-1: 0] sys_sel_i , //!< bus write byte select
input sys_wen_i , //!< bus write enable
input sys_ren_i , //!< bus read enable
output reg [ 32-1: 0] sys_rdata_o , //!< bus read data
output reg sys_err_o , //!< bus error indicator
output reg sys_ack_o //!< bus acknowledge signal
);
//---------------------------------------------------------------------------------
//
// System bus connection
reg[31:0] data;
always @(posedge sys_clk_i) begin
if (sys_rstn_i == 1'b0) begin
data = 32'h0;
end
else begin
if (sys_wen_i) begin
data <= sys_wdata_i[32-1:0] ;
end
end
end
always @(*) begin
sys_err_o <= 1'b0 ;
casez (sys_addr_i[20:0])
20'h0????: begin sys_ack_o <= 1'b1; sys_rdata_o <= {data} ; end
20'h1????: begin sys_ack_o <= 1'b1; sys_rdata_o <= {data} ; end
20'h2????: begin sys_ack_o <= 1'b1; sys_rdata_o <= {data} ; end
20'h3????: begin sys_ack_o <= 1'b1; sys_rdata_o <= {data} ; end
20'h4????: begin sys_ack_o <= 1'b1; sys_rdata_o <= {data} ; end
20'h5????: begin sys_ack_o <= 1'b1; sys_rdata_o <= {data} ; end
20'h6????: begin sys_ack_o <= 1'b1; sys_rdata_o <= {data} ; end
20'h7????: begin sys_ack_o <= 1'b1; sys_rdata_o <= {data} ; end
20'h8????: begin sys_ack_o <= 1'b1; sys_rdata_o <= {data} ; end
20'h9????: begin sys_ack_o <= 1'b1; sys_rdata_o <= {data} ; end
20'ha????: begin sys_ack_o <= 1'b1; sys_rdata_o <= {data} ; end
20'hb????: begin sys_ack_o <= 1'b1; sys_rdata_o <= {data} ; end
20'hc????: begin sys_ack_o <= 1'b1; sys_rdata_o <= {data} ; end
20'hd????: begin sys_ack_o <= 1'b1; sys_rdata_o <= {data} ; end
20'he????: begin sys_ack_o <= 1'b1; sys_rdata_o <= {data} ; end
20'hf????: begin sys_ack_o <= 1'b1; sys_rdata_o <= {data} ; end
default : begin sys_ack_o <= 1'b1; sys_rdata_o <= 32'h0 ; end
endcase
end
endmodule
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red_pitaya_free i_free
(
.clk_i (adc_clk), // clock
.rstn_i (adc_rstn), // reset - active low
// System bus
.sys_clk_i ( sys_clk ), // clock
.sys_rstn_i ( sys_rstn ), // reset - active low
.sys_addr_i ( /*sys_addr*/ 32'h40600000 ), // address
.sys_wdata_i ( /*sys_wdata*/ 32'h1fff ), // write data
.sys_sel_i ( sys_sel ), // write byte select
.sys_wen_i ( sys_wen[6] ), // write enable
.sys_ren_i ( sys_ren[6] ), // read enable
.sys_rdata_o ( sys_rdata[ 6*32+31: 6*32]), // read data
.sys_err_o ( sys_err[6] ), // error indicator
.sys_ack_o ( sys_ack[6] ) // acknowledge signal
);
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redpitaya> monitor 0x40600000
0x000000cc
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redpitaya> monitor 0x40600000 0x00001fff
redpitaya> monitor 0x40600000
0x00001fff
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redpitaya> monitor 0x40600000 0x00001ccc
redpitaya> monitor 0x40600000
0x00001fff
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redpitaya> monitor 0x40600000
0x00001fff
redpitaya> monitor 0x40600004
0x00001fff
redpitaya> monitor 0x40600008
0x00001fff
redpitaya> monitor 0x4060000c
0x00001fff
redpitaya> monitor 0x40600010
0x00001fff
redpitaya> monitor 0x406f0010
0x00001fff
redpitaya> monitor 0x406ffff0
0x00001fff
redpitaya> monitor 0x406ffffc
0x00001fff