PID Control with Slow Analog Inputs

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lw58
Posts: 7
Joined: Mon Jul 06, 2015 11:20 am

PID Control with Slow Analog Inputs

Post by lw58 » Wed Jul 22, 2015 10:18 pm

Hello all,

The Red Pitaya's PID controller works well for the fast analog inputs and outputs. Would it be possible to extend the functionality to the slow analog inputs as well? Why were the slow analog inputs/outputs not included when developing the Scope+PID web app?

Thanks.

Nils Roos
Posts: 1441
Joined: Sat Jun 07, 2014 12:49 pm
Location: Königswinter

Re: PID Control with Slow Analog Inputs

Post by Nils Roos » Thu Jul 23, 2015 7:09 pm

Hi,
From a logic design perspective, the auxiliary inputs and outputs could be connected to an upgraded pid controller. Maybe not all of them with full mimo configuration, due to resource constraints, but at least some.

I don't know if it would be useful, though, seeing as the auxiliary signals update at a rate three orders of magnitude slower than the fast inputs/outputs.
If that's not a concern for you, try it out ;)

lw58
Posts: 7
Joined: Mon Jul 06, 2015 11:20 am

Re: PID Control with Slow Analog Inputs

Post by lw58 » Tue Jul 28, 2015 10:39 pm

Thanks. I do not actually need MIMO, all will be SISO.

The reason why it is useful is to maximise the number of PID controllers that I can get out of one RP.

I have been reading the FPGA verilog files and I am confused as to how to obtain data from the slow analog inputs. In the red_pitaya_analog.v module there is the ability to read from the fast (14-bit) ADCs with the following ports:

// user interface
output [ 14-1: 0] adc_dat_a_o , //!< ADC CHA data
output [ 14-1: 0] adc_dat_b_o , //!< ADC CHB data

I believe there is also the ability to send user data to both the slow and fast DACs with the following ports:

input [ 14-1: 0] dac_dat_a_i , //!< DAC CHA data
input [ 14-1: 0] dac_dat_b_i , //!< DAC CHB data

input [ 24-1: 0] dac_pwm_a_i , //!< DAC PWM CHA
input [ 24-1: 0] dac_pwm_b_i , //!< DAC PWM CHB
input [ 24-1: 0] dac_pwm_c_i , //!< DAC PWM CHC
input [ 24-1: 0] dac_pwm_d_i , //!< DAC PWM CHD

However I do not see any capability to read data from the 4 slow analog 12-bit ADCs? Is this correct? How would I be able to obtain the data coming in from the slow ADCs?

I believe it may have something to do with the XADC module which is instantiated within the red_pitaya_ams.v module. Is there any documentation available about the XADC module?

I hope this makes sense, I am completely new to verilog!

Nils Roos
Posts: 1441
Joined: Sat Jun 07, 2014 12:49 pm
Location: Königswinter

Re: PID Control with Slow Analog Inputs

Post by Nils Roos » Fri Jul 31, 2015 12:55 am

The reason you did not find them is that they are not eported from the red_pitaya_ams module.

The registers adc_[a-d]_r contain the most recent sample from channel A-D at all times. They are only connected to the IO addresses 0x40400000-0x4040000c at the moment, but you could route them up to red_pitaya_top and from there to your additional PID controllers.

lw58
Posts: 7
Joined: Mon Jul 06, 2015 11:20 am

Re: PID Control with Slow Analog Inputs

Post by lw58 » Mon Aug 03, 2015 4:06 pm

Thanks, this works well!

I have another question regarding writing data to the slow DACs. Suppose I now have a 12-bit output from my PID module and I want to input this to the slow DACs. Do I need to pad it with zeros to become a 24-bit number and then pass it into the red_pitaya_analog module as the dac_pwm_(a-d)_i inputs?

I read the other forum posts about how the PWM works but i'm still unsure how to practically write data to the slow dacs.

Nils Roos
Posts: 1441
Joined: Sat Jun 07, 2014 12:49 pm
Location: Königswinter

Re: PID Control with Slow Analog Inputs

Post by Nils Roos » Wed Aug 05, 2015 12:11 pm

It's a bit more complicated than that, you can use the most significant 8bit as they are, but you need to expand the lower 4bit into a 16bit value to get the full resolution. It would be something like:

Code: Select all

wire [11:0] sample_i;
always @(posedge clk_i) begin
    dac_a_r[23:16] <= sample_i[11:4];
    case (sample_i[3:0])
    4'd0 : dac_a_r[15:0] <= 16'b0000000000000000;
    4'd1 : dac_a_r[15:0] <= 16'b0000000000000001;
    4'd2 : dac_a_r[15:0] <= 16'b0000000100000001;
    4'd3 : dac_a_r[15:0] <= 16'b0000100000100001;
    4'd4 : dac_a_r[15:0] <= 16'b0001000100010001;
    4'd5 : dac_a_r[15:0] <= 16'b0010010010010001;
    4'd6 : dac_a_r[15:0] <= 16'b0010100100101001;
    4'd7 : dac_a_r[15:0] <= 16'b0101010010101001;
    4'd8 : dac_a_r[15:0] <= 16'b0101010101010101;
    4'd9 : dac_a_r[15:0] <= 16'b1010101101010110;
    4'd10: dac_a_r[15:0] <= 16'b1101011011010110;
    4'd11: dac_a_r[15:0] <= 16'b1101101101101110;
    4'd12: dac_a_r[15:0] <= 16'b1110111011101110;
    4'd13: dac_a_r[15:0] <= 16'b1111011111011110;
    4'd14: dac_a_r[15:0] <= 16'b1111111011111110;
    4'd15: dac_a_r[15:0] <= 16'b1111111111111110;
    endcase
end

lw58
Posts: 7
Joined: Mon Jul 06, 2015 11:20 am

Re: PID Control with Slow Analog Inputs

Post by lw58 » Mon Aug 10, 2015 6:56 pm

Thanks Nils. So to clarify, if the 8 most significant bits are all 1's then the PWM duty cycle is 100% and if the 8 most significant bits are all 0's then the PWM duty cycle is 0%?

Nils Roos
Posts: 1441
Joined: Sat Jun 07, 2014 12:49 pm
Location: Königswinter

Re: PID Control with Slow Analog Inputs

Post by Nils Roos » Tue Aug 11, 2015 11:20 am

That statement is correct, but you get 100% duty cycle at any value >= 156 in the upper 8 bits.

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