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cat bitstram.bit > /dev/xdevcfg
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cat bitstram.bit > /dev/xdevcfg
But I don't agree with it because ofYou need to instantiate a Zynq "PS7" component in your design, that is the interface between the Linux SoC part and the FPGA fabric, there is also a wizard in Vivado to configure this. If this component is not in the design then programming the bitstream crashes the SoC.
If the Linux on Red Pitaya also assumes the presence of any AXI slaves on the FPGA fabric side, omitting these from the design might also cause a lock up, but this is less likely to be the problem.
Are Any other thoughts?David, great thank you dir your reply. Are you sure that ps7 is needed in all zyxq 7 projects? Exactly this example has no any interaction with PS7 CPU. No AXI and no other components. Only clock, from external source, frequency divider and output port for LED. FPGA fabric is self sufficient. Why PS7 is needed for not hunging?
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set_property IOSTANDARD LVCMOS33 [get_ports led_0]
set_property SLEW SLOW [get_ports led_0]
set_property DRIVE 4 [get_ports led_0]
set_property PACKAGE_PIN J14 [get_ports led_0]
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity blink is
port (
clk : in std_logic;
led : out std_logic
);
end blink;
architecture Behavioral of blink is
signal state : std_logic;
-- 100Mhz, 10ns, 1s => 10E8
constant max_count : natural := 10000000;
begin
clk_p : process(clk)
variable count : natural range 0 to max_count;
begin
if rising_edge(clk) then
if count < max_count/2 then
-- 1/2s on
state <= '1';
count := count + 1;
elsif count < max_count then
state <= '0';
count := count + 1;
elsif count = max_count then
state <= '0';
count := 0;
end if;
end if;
end process clk_p;
led <= state;
end Behavioral;
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