External clocking frequency range

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Sean McKee
Posts: 3
Joined: Tue May 19, 2020 4:03 pm

External clocking frequency range

Post by Sean McKee » Fri Oct 16, 2020 5:28 pm

Hello all,

I've seen a lot of posts about using an external clock for the ADC and associated logic, and I understand the hardware modifications that will be required, as described here: https://redpitaya.readthedocs.io/en/lat ... xtADC.html
I've seen some older posts inquiring about whether a specific frequency will work, and the answer is usually "maybe."

So, my question is, what frequencies have users tried, what ranges worked immediately, and which required further modifications?

I would like to clock the 125-14 at ~100MHz to avoid aliasing of a particular signal. It is my understanding that this will clock the ADCs directly, which will in turn clock the FPGA logic. I am not planning on using the DACs. Can I expect that the code which is currently running on the FPGA at 125MHz will behave exactly the same, just at 100 MHz instead of 125?

Will the PS-FPGA interface be affected? I am running software on the linux side which polls the FPGA BRAM registers. I'm hoping that this will not need to be altered?

bma
Posts: 6
Joined: Wed Sep 23, 2020 9:54 am

Re: External clocking frequency range

Post by bma » Wed Oct 21, 2020 7:08 pm

Hi Sean,

It is working with a 100MHz, 7dBm reference signal, but you can't swipe the reference frequency too fast.
Yes, the behave is the same.
The data are added to the BRAM buffer only on data clock rising edges, so, there is no double values.

BR

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