How are EMIO signals connected to package pins?

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How are EMIO signals connected to package pins?

Post by boze » Sat Jul 31, 2021 7:47 pm

I am trying to figure out how the GPIO signals in the Zynq PS (via EMIO) are connected to the specific package pins listed in the XDC file when the GPIO_0 port on the PS is just connected to a block design port called GPIO (i.e. not a signal name in the XDC file).
For instance, when using the "Classic" FPGA project, pin "DIO0_P" on connector E1 is connected to package pin G17 which is linked to signal "exp_p_io[0]" in the XDC file. According to the developer's guide 3.2.11 (GPIO), this pin can be accessed in the user-space by sysfs index 968 (906+54+8). I have also verified that I can control this pin from the Linux terminal How (and where) does "exp_p_io[0]" get connected to EMIO[8]?

I have a modified version of the block design where the LEDs and DIO0_P - DIO3_P are being controlled from the PL. I have changed the number of EMIO signals to 12, and I assumed that DIO4_P would now be accessed by sysfs index 960 (906+54+0), but this doesn't seem to work. By shear brute force and luck, I have figured out that DIO7_N is linked to sysfs index 971, and DIO6_N is linked to index 969. These are the only two I can control, and their indexes don't make sense to me. I'm thinking that the link between the XDC file and the EMIO is my problem.

This seems like something simple, but I haven't been able to find any info about it online - maybe I'm using the wrong search terms.

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Re: How are EMIO signals connected to package pins?

Post by redpitaya » Thu Aug 12, 2021 9:25 am

depending on the model of the board you have you can find the electronic development schematic in our online documentation.

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