Sampling at a fixed 75MHz?

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Sampling at a fixed 75MHz?

Post by ph2thet » Tue Jun 14, 2022 1:17 pm

Is it possible to sample at 75MHz? Do the ADC and FPGA have to run at the same clock? I have a very good 25, 37.5 or 50MHz clock source. Can the FPGA do the doubling for the ADC?

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Re: Sampling at a fixed 75MHz?

Post by redpitaya » Wed Jun 15, 2022 5:59 pm

You can use an external clock with 75 MHz if you have one.

ADC and DAC run on the same clock.

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Re: Sampling at a fixed 75MHz?

Post by jbracegirdle » Wed Jun 15, 2022 7:44 pm

The Red Pitaya Docs have details about how to modify a Red Pitaya STEMlab 125-14 to use an external ADC clock. If you're looking to buy a new Red Pitaya there is a version with the external ADC clock modifications already done to it.

I've not tried an external or FPGA based ADC & DAC clock. I've just stayed with the on board one for now, but it's interesting looking at the docs to think of future project ideas.

The Frequency Counter FPGA lessons 5 originally by Anton Potočnik shows a good basic example of using the ADC and DAC and communication to the Linux CPU of of the board. It shows different clocks for the ADC and FPGA, so you could run the ADC at 75MHz and the FPGA fabric at 150MHZ.

You can even change the FPGA fabric clock while the board is booted using the following Linux terminal commands. The commands need root access. The clock frequency can be set from 100000 to 250000000. 150MHz is used in the example below:

Code: Select all

test -d $devcfg/fclk/fclk0 || echo fclk0 > $devcfg/fclk_export
echo 0 > $devcfg/fclk/fclk0/enable
echo 150000000 > $devcfg/fclk/fclk0/set_rate
echo 1 > $devcfg/fclk/fclk0/enable
Last edited by jbracegirdle on Wed Jun 22, 2022 4:59 pm, edited 1 time in total.

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Re: Sampling at a fixed 75MHz?

Post by ph2thet » Wed Jun 22, 2022 2:56 pm

This is great news! The fact that the FPGA clock can go up compared to an external clock. Love that.

Great example!! Thanks

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