SATA-Connectors: Length Matched? LVDS?

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std_logic
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Joined: Sat Jan 07, 2023 4:50 pm

SATA-Connectors: Length Matched? LVDS?

Post by std_logic » Thu Jan 12, 2023 11:44 pm

Hello!

I want to use the SATA connectors to receive data from a sensor with an LVDS clock lane and 2-3 LVDS data lanes.
This means one of the clock capable pair of one of the connectors would be used for the clock, and the other three pairs would be used for data lanes. At higher data rates it would be very helpfull if the trace length from FPGA pin to the SATA connector is the same for all 4 differential lanes.
Is that the case on the Redpitaya? Or are only the two differential lanes of each connector length matched?

And would LVDS be possible? Officially the Zynq only does "LVDS25" on its HR bank, and for that the bank needs to be powered from 2.5 V.
On the Redpitaya 14-125 the bank with the SATA connectors is powered from just 1.8 V. But according to this page it should still be possible: https://support.xilinx.com/s/article/43 ... uage=en_US
In my case the LVDS voltage is within the VIN requirement of the bottom chart, and the differential pairs that lead to the SATA connectors are terminated with 100 Ohm on the Redpitaya.

Does anyone have experience with receiving LVDS on those SATA connectors?

Thank you!

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redpitaya
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Re: SATA-Connectors: Length Matched? LVDS?

Post by redpitaya » Mon Jan 16, 2023 7:47 pm

Hello std_logic,

The SATA data line pairs on a connector are matched. The data lines on a single connector should be matched, but we need to open the Altium project and measure it to be sure.

You could try using the IDELAY2 module on the FPGA, which is used for matching the lines between each other.

You can try using the solution presented in the Xilinx article at your own risk.

std_logic
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Joined: Sat Jan 07, 2023 4:50 pm

Re: SATA-Connectors: Length Matched? LVDS?

Post by std_logic » Mon Jan 16, 2023 11:11 pm

Thank you for the reply, I will have a look at the Delay-module!

juretrn
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Joined: Tue Nov 16, 2021 11:38 am

Re: SATA-Connectors: Length Matched? LVDS?

Post by juretrn » Mon Jan 23, 2023 11:33 am

Note that using IDELAYE2 is not that easy.
As an example, you can have look at

https://github.com/RedPitaya/RedPitaya- ... aya_top.sv

To use it, you need an IDELAYCTRL and IDELAYE2.
IDELAYCTRL requires a 200 MHz clock and an appropriate reset.
I suggest using it in fixed mode, since the delay between the lines does not change.
One delay tap is 78 ps, and up to 31 taps of delay are available.

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