FPGA AXI GP0 bus <-> PS memory map ? [handover]

[pita]

Hello folks !

From the FPGA side, the last Verilog module before PS is system_wrapper.
But how are the associated electrical signals like gp0_maxi_rdata of system_wrapper being interpreted and connected
to the FPGA memory map (/fpga/doc/RedPitaya_HDL_memory_map.odt) ? I mean.. what driver/module is responsible for that ?

From the Cortex A9 side I can use /dev/mem and mmap() to write to physical addresses yes I know that,
but here also when I write to a corresponding address in physical space who does the handover
back to axi gp0 wires (and serial encoding) ? Who creates the layout of the memory map and divides it into
housekeeping, oscilloscope, etc. regions ?

The deeper I get the more I (really) love this board.
Clean sourcecode ! But at this point, I'm stuck.
I'd appreciate any help.

Best regards
pita

[Nils Roos]

Hi pita,

how are the associated electrical signals like gp0_maxi_rdata of system_wrapper being interpreted and connected
to the FPGA memory map ... what driver/module is responsible for that ?

No driver or module is involved in the process, it is all handled on the level of internal AXI-busses and -interconnects.

Take a look at Figure 5-1 in the ZYNQ technical reference manual. You'll find the ARM cores (Cortex A9) in the upper left. They are connected to the master interconnect via SCU and L2 cache controller. The master interconnect has connections to the General purpose AXI controllers and M_AXI_GP0 is the bus that is connected to the gp0_maxi_* signals in system_wrapper.v .

in physical space who does the handover back to axi gp0 wires (and serial encoding) ?

The master interconnect does that. When you activate the AXI GP0 master interface in the ZYNQ IP configuration, you have to define an address mapping for it. This mapping tells the master interconnect (and SCU and L2C) to forward accesses to addresses in that region to the AXI GP0 master. In the Red Pitaya, the address region from 0x40000000 to 0x7fffffff is mapped to AXI GP0.

Who creates the layout of the memory map and divides it into housekeeping, oscilloscope, etc. regions ?

This happens in red_pitaya_top.v in the part labelled with "system bus decoder & multiplexer". The system bus - which is connected to AXI GP0 through the module axi_slave in axi_slave.v - is split into 8 regions and these regions are connected to the housekeeping, scope, etc. modules.

Has it become clearer now ?
Cheers
Nils

[pita]

Yes !
Definitely !

I also found that line now thanks to Your help:

Code: Select all

<spirit:addressOffset>0x40000000</spirit:addressOffset>
 <spirit:range>1G</spirit:range>

It's in /fpga/ip/system.bd.
(just in case someone else should be interested)


Thank You very much !

Best regards
pita

[lhochstetter]

(Found this thread while searching for answers to a similar question ...)

What does the 0x40000000 to 0x7fffffff stand for?

I do understand that this are hexadecimal numbers describing the memory offsets for the parent memory space for the memory spaces of the modules.

As far as I can tell the Redpitaya DDR RAM has a size of 512 mega bytes (536 870 912 bytes) / 4 giga bits but 0x7fffffff (=2 147 483 647) is way larger than 512 mega bytes in terms of address range, is it not?

How does this work without throwing tons of errors? Do I miss something like swapping RAM to the SD Card?

[Nils Roos]

I do understand that this are hexadecimal numbers describing the memory offsets for the parent memory space for the memory spaces of the modules.

Ok, first a bit of "microprocessor architecture 101" (much simplified, leaving out such things as MMU):
A processor has an address bus which it uses to announce the target of its data exchanges. All possible addresses on that bus together comprise the address space - in case of the RP, the address space is 0x00000000 - 0xffffffff (buswidth is 32bit and there are no "holes" in the address space).

Multiple devices can be connected to that address bus, and each device observes the bus to see if the target address lies within its allotted range. The DDR controller (on the RP) is responsible for the region 0x00000000 - 0x1ffffffff, and most of the integrated peripherals (ethernet controller, UARTs, USB controller, etc) lie somewhere above 0xe0000000.

So, "memory space" is the wrong concept when thinking about this, the memory is just another device on a larger, shared address space. The AXI GP0 interface that connects to the FPGA logic is another such device, and it is configured to occupy the address region 0x40000000-0x7fffffff.

PS: If the processor tries to access an address where no device is listening, errors do in fact happen - bad ones usually.

[lhochstetter]

Oh ... I see, thanks.

And the memory mapping is used to map address of the address bus to memory addresses and anything written to the memory addresses is then forwarded to the bus addresses (i.e. FPGA register, if they are mapped to the memory)?

[Nils Roos]

The underlying mechanism is a bit more complicated, but you got the right idea.

Programs that run on the ARM cores can't use the address bus directly, because the MMU (memory management unit) lies in between. It enables such things as virtual memory and memory protection mechanisms by dynamically translating logical addresses that the cores use into physical addresses that point to actual memory locations.
The only way for user-space applications to access a specific physical address is to use a mapping on /dev/mem, a device driver that represents the linear 32bit address space as a file. You open the file and request a mapping to a section of it, and the position inside the file translates 1:1 into a physical address.