I teste the hold TTL input today and it worked perfectly (see screenshot ).
![Image](http://abload.de/img/scope_42e7uac.png)
yellow:inputsignal; green:integrator output; blue:TTL-signal
Thanks for sharing your code and for your help!
Best wishes Florian
Hey Claire,ClaireE47 wrote:Hey, this has my edits to the C code (Applications/MyPID/src) and the HTML (Applications/MyPID/index.html) for the software trigger, and the Verilog edits (FPGA/release1/fpga/code/).
https://www.dropbox.com/sh/rwjmzs183ls9 ... AwFZa?dl=0
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root@rp-f04d8a:~/tmp/FPGA/release1/fpga/vivado/red_pitaya.runs/impl_1#
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cat /tmp/FPGA/release1/fpga/vivado/red_pitaya.runs/impl_1/red_pitaya_top.bit >/dev/xdevcfg
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red_pitaya_top.bit root@@192.168.11.25:/tmp
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cat /tmp/red_pitaya_top.bit >/dev/xdevcfg
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