PID Integrator Hold
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- Posts: 10
- Joined: Wed Jul 02, 2014 9:05 am
Re: PID Integrator Hold
Hi Claire,
I teste the hold TTL input today and it worked perfectly (see screenshot ).
yellow:inputsignal; green:integrator output; blue:TTL-signal
Thanks for sharing your code and for your help!
Best wishes Florian
I teste the hold TTL input today and it worked perfectly (see screenshot ).
yellow:inputsignal; green:integrator output; blue:TTL-signal
Thanks for sharing your code and for your help!
Best wishes Florian
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- Posts: 20
- Joined: Thu Oct 02, 2014 8:26 am
Re: PID Integrator Hold
That looks awesome! I'm so glad
All the best,
Claire
All the best,
Claire
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- Posts: 54
- Joined: Mon Feb 06, 2017 12:31 pm
Re: PID Integrator Hold
Hey Claire,ClaireE47 wrote:Hey, this has my edits to the C code (Applications/MyPID/src) and the HTML (Applications/MyPID/index.html) for the software trigger, and the Verilog edits (FPGA/release1/fpga/code/).
https://www.dropbox.com/sh/rwjmzs183ls9 ... AwFZa?dl=0
it is interesting topic for me that you successfully made PID algorithm.
i already learned about generate .bit and .bin using vivado and labtools
Now, i want to try to make PID.
I did try download your dropbox link, but the dropbox link is disabled.
please, could you upload again
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- Posts: 1
- Joined: Mon Jun 26, 2017 11:31 pm
Re: PID Integrator Hold
Hi Claire
I am also interested in your PID sample/hold-code -- the results from fromage looks good!
I know the post is old. Unfortunately, no one else has touched the subject since (as far as I can find).
As being new to RedPitaya and FPGA, I would be very happy if you could share your code once again
I looked at the code you posted so far in the thread, but I would like to see your final code.
So Claire, I hope you are still there... Even just the FPGA code without the C and HTML would be good!
Best,
Thomas
I am also interested in your PID sample/hold-code -- the results from fromage looks good!
I know the post is old. Unfortunately, no one else has touched the subject since (as far as I can find).
As being new to RedPitaya and FPGA, I would be very happy if you could share your code once again
I looked at the code you posted so far in the thread, but I would like to see your final code.
So Claire, I hope you are still there... Even just the FPGA code without the C and HTML would be good!
Best,
Thomas
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- Posts: 20
- Joined: Thu Oct 02, 2014 8:26 am
Re: PID Integrator Hold
Hi Amin and Thomas,
Sorry about the dropbox confusion - I must have removed the code at some point. It's been a while since I've thought about this project but I think that this should be sufficient code... If there's anything missing just give me a yell and I'll have a look.
Cheers,
Claire
Sorry about the dropbox confusion - I must have removed the code at some point. It's been a while since I've thought about this project but I think that this should be sufficient code... If there's anything missing just give me a yell and I'll have a look.
Cheers,
Claire
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- Posts: 1
- Joined: Wed Jan 27, 2016 12:18 pm
Re: PID Integrator Hold
Is there any reason that the hold signals have to go through house keeping module, can I directly use two pins in Expansion connectors "[8-1:0] exp_p_io" instead?
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- Posts: 54
- Joined: Mon Feb 06, 2017 12:31 pm
Re: PID Integrator Hold
ClaireE47,
I already copy your FPGA folder to tmp in git of redpitaya in eclipse.
and then i search file bit that i found red_pitaya_top.bit in
i tried compile this red_pitaya_top.bit using
But i did not get signal respon in the output of DIO0_P and DIO1_P. i tried connect these output using oscilloscope.
Is it correct if i just copy into tmp folder in respitory eclipse?
Can you explain step by step of how to copy into respitory redpitaya in eclipse?
Also can i edit this FPGA folder in vivado? I already open the RedPitaya_with_Hold\FPGA\release1\fpga\vivado\vivado.xpr in vivado 2016.3 but i cannot generate bit stream.
sorry i am still learn about vivado and linux
Sincerely,
Amin
I already copy your FPGA folder to tmp in git of redpitaya in eclipse.
and then i search file bit that i found red_pitaya_top.bit in
Code: Select all
root@rp-f04d8a:~/tmp/FPGA/release1/fpga/vivado/red_pitaya.runs/impl_1#
i tried compile this red_pitaya_top.bit using
Code: Select all
cat /tmp/FPGA/release1/fpga/vivado/red_pitaya.runs/impl_1/red_pitaya_top.bit >/dev/xdevcfg
Is it correct if i just copy into tmp folder in respitory eclipse?
Can you explain step by step of how to copy into respitory redpitaya in eclipse?
Also can i edit this FPGA folder in vivado? I already open the RedPitaya_with_Hold\FPGA\release1\fpga\vivado\vivado.xpr in vivado 2016.3 but i cannot generate bit stream.
sorry i am still learn about vivado and linux
Sincerely,
Amin
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- Posts: 54
- Joined: Mon Feb 06, 2017 12:31 pm
Re: PID Integrator Hold
ClaireE47,
I can generate bitstream your RedPitaya_with_Hold\FPGA\release1\fpga\vivado\vivado.xpr using vivado 2013.3.
after that i copy red_pitaya_top.bit from FPGA/release1/fpga/vivado/red_pitaya.runs/impl_1 into eclipse redpitaya/tmp.
But when i executed using scp and , i only get respon blink led in LED0.
I did not get respon signal output in DIO0_P and DIO1_P.
Regards,
Amin
I can generate bitstream your RedPitaya_with_Hold\FPGA\release1\fpga\vivado\vivado.xpr using vivado 2013.3.
after that i copy red_pitaya_top.bit from FPGA/release1/fpga/vivado/red_pitaya.runs/impl_1 into eclipse redpitaya/tmp.
But when i executed using scp
Code: Select all
red_pitaya_top.bit root@@192.168.11.25:/tmp
Code: Select all
cat /tmp/red_pitaya_top.bit >/dev/xdevcfg
I did not get respon signal output in DIO0_P and DIO1_P.
Regards,
Amin
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