Controlling the DAC output
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- Posts: 7
- Joined: Tue Jul 12, 2016 12:17 am
Controlling the DAC output
Hi,
I am new to Red Pitaya and Verilog programming.
Right now I am trying to use the Blink LED tutorial project to familiarize myself with Red Pitaya. I am hoping to build on the existing code and control the DAC ouput, for example outputting constant voltage on one of the analog output.
I have tried modifying the definition of dac_a and dac_b in the top file, but the output is always zero. I would really appreciate if someone could give me an example.
Thanks!
I am new to Red Pitaya and Verilog programming.
Right now I am trying to use the Blink LED tutorial project to familiarize myself with Red Pitaya. I am hoping to build on the existing code and control the DAC ouput, for example outputting constant voltage on one of the analog output.
I have tried modifying the definition of dac_a and dac_b in the top file, but the output is always zero. I would really appreciate if someone could give me an example.
Thanks!
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- Posts: 1441
- Joined: Sat Jun 07, 2014 12:49 pm
- Location: Königswinter
Re: Controlling the DAC output
Hi,
to output a constant to the DAC with the tutorial codebase, you would add something like
to red_pitaya_top after the declaration of dac_a and dac_b.
to output a constant to the DAC with the tutorial codebase, you would add something like
Code: Select all
always @(posedge adc_clk) begin
if (~adc_rstn) begin
dac_a <= 14'h0;
dac_b <= 14'h0;
end else begin
dac_a <= 14'h1234;
dac_b <= 14'h2345;
end
end
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Re: Controlling the DAC output
Thanks for the reply! Unfortunately that code didn't seem to work, both output voltage channels remain at either 0 or +/-1, randomly switching between the values at approximately half-hour intervals.
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- Posts: 1441
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Re: Controlling the DAC output
When I upgrade the tutorial project to Vivado 2016.2, then insert the above code into red_pitaya_top.v, generate a new bitstream from it, and load it on the Red Pitaya, I can measure 0.56V on channel A output and -0.9V on channel B, as expected.
Make sure that the bitstream was generated successfully. There is one additional step after upgrading that needs to be done, changing the red_pitaya.xdc, lines 134,135, to
(without that, the step "Generate Bitstream" will fail)
Make sure that the bitstream was generated successfully. There is one additional step after upgrading that needs to be done, changing the red_pitaya.xdc, lines 134,135, to
Code: Select all
set_property IOSTANDARD LVCMOS33 [get_ports {vinp_i[*]}]
set_property IOSTANDARD LVCMOS33 [get_ports {vinn_i[*]}]
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- Posts: 7
- Joined: Tue Jul 12, 2016 12:17 am
Re: Controlling the DAC output
Hi, Nils,
Thanks for the response! Could you explain a litter bit what these two lines of modification do?
Thanks.
Thanks for the response! Could you explain a litter bit what these two lines of modification do?
Thanks.
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- Posts: 1441
- Joined: Sat Jun 07, 2014 12:49 pm
- Location: Königswinter
Re: Controlling the DAC output
Between 2013.3 and 2014.1 Vivado was changed from requiring a differential IO standard being defined for the XADC input pins to requiring a single-ended one. Using the wrong one leads to errors during implementation of a design and termination of the bitstream generation. It is just a formality, but getting it wrong leads to a failed build and no updated bitstream. The tutorial project was designed with Vivado 2013.3 and thus you need to do the change in order to build the project with a current version.
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- Joined: Mon Feb 06, 2017 12:31 pm
Re: Controlling the DAC output
Hi Nils Roos,
I have been use this code:
I use basic basic project from this link http://redpitaya.com/examples-new/fpga- ... -tutorial/:
http://www.dropbox.com/s/j26fb3pmlfmttx ... e.zip?dl=1
I use vivado 2013.
without this modified redpitaya.xdc:
I can generate bitstream. i load bit into my redpitaya/tmp and run red_pitaya_top.bit.
But i can not get response signal generator in DAC1.
If i change TMDS_33 into LVCMOS33, i got error when generate bitsream like this comment below:
ERROR: [Drc 23-20] Rule violation (IOSTDTYPE-1) IOStandard Type - I/O port vinn_i[0] is Differential but has an IOStandard of LVCMOS33 which can only support Single-Ended
ERROR: [Drc 23-20] Rule violation (IOSTDTYPE-1) IOStandard Type - I/O port vinn_i[1] is Differential but has an IOStandard of LVCMOS33 which can only support Single-Ended
ERROR: [Drc 23-20] Rule violation (IOSTDTYPE-1) IOStandard Type - I/O port vinn_i[2] is Differential but has an IOStandard of LVCMOS33 which can only support Single-Ended
ERROR: [Drc 23-20] Rule violation (IOSTDTYPE-1) IOStandard Type - I/O port vinn_i[3] is Differential but has an IOStandard of LVCMOS33 which can only support Single-Ended
ERROR: [Drc 23-20] Rule violation (IOSTDTYPE-1) IOStandard Type - I/O port vinn_i[4] is Differential but has an IOStandard of LVCMOS33 which can only support Single-Ended
ERROR: [Drc 23-20] Rule violation (IOSTDTYPE-1) IOStandard Type - I/O port vinp_i[0] is Differential but has an IOStandard of LVCMOS33 which can only support Single-Ended
ERROR: [Drc 23-20] Rule violation (IOSTDTYPE-1) IOStandard Type - I/O port vinp_i[1] is Differential but has an IOStandard of LVCMOS33 which can only support Single-Ended
ERROR: [Drc 23-20] Rule violation (IOSTDTYPE-1) IOStandard Type - I/O port vinp_i[2] is Differential but has an IOStandard of LVCMOS33 which can only support Single-Ended
ERROR: [Drc 23-20] Rule violation (IOSTDTYPE-1) IOStandard Type - I/O port vinp_i[3] is Differential but has an IOStandard of LVCMOS33 which can only support Single-Ended
ERROR: [Drc 23-20] Rule violation (IOSTDTYPE-1) IOStandard Type - I/O port vinp_i[4] is Differential but has an IOStandard of LVCMOS33 which can only support Single-Ended[/code]
Could you give me some advice, so i could figure out the issue.
Thanks
I have been use this code:
Code: Select all
always @(posedge adc_clk) begin
if (~adc_rstn) begin
dac_a <= 14'h0;
dac_b <= 14'h0;
end else begin
dac_a <= 14'h1234;
dac_b <= 14'h2345;
end
end
I use basic basic project from this link http://redpitaya.com/examples-new/fpga- ... -tutorial/:
http://www.dropbox.com/s/j26fb3pmlfmttx ... e.zip?dl=1
I use vivado 2013.
without this modified redpitaya.xdc:
Code: Select all
set_property IOSTANDARD LVCMOS33 [get_ports {vinp_i[*]}]
set_property IOSTANDARD LVCMOS33 [get_ports {vinn_i[*]}]
But i can not get response signal generator in DAC1.
If i change TMDS_33 into LVCMOS33, i got error when generate bitsream like this comment below:
Code: Select all
ERROR: [Drc 23-20] Rule violation (IOSTDTYPE-1) IOStandard Type - I/O port vinn_i[1] is Differential but has an IOStandard of LVCMOS33 which can only support Single-Ended
ERROR: [Drc 23-20] Rule violation (IOSTDTYPE-1) IOStandard Type - I/O port vinn_i[2] is Differential but has an IOStandard of LVCMOS33 which can only support Single-Ended
ERROR: [Drc 23-20] Rule violation (IOSTDTYPE-1) IOStandard Type - I/O port vinn_i[3] is Differential but has an IOStandard of LVCMOS33 which can only support Single-Ended
ERROR: [Drc 23-20] Rule violation (IOSTDTYPE-1) IOStandard Type - I/O port vinn_i[4] is Differential but has an IOStandard of LVCMOS33 which can only support Single-Ended
ERROR: [Drc 23-20] Rule violation (IOSTDTYPE-1) IOStandard Type - I/O port vinp_i[0] is Differential but has an IOStandard of LVCMOS33 which can only support Single-Ended
ERROR: [Drc 23-20] Rule violation (IOSTDTYPE-1) IOStandard Type - I/O port vinp_i[1] is Differential but has an IOStandard of LVCMOS33 which can only support Single-Ended
ERROR: [Drc 23-20] Rule violation (IOSTDTYPE-1) IOStandard Type - I/O port vinp_i[2] is Differential but has an IOStandard of LVCMOS33 which can only support Single-Ended
ERROR: [Drc 23-20] Rule violation (IOSTDTYPE-1) IOStandard Type - I/O port vinp_i[3] is Differential but has an IOStandard of LVCMOS33 which can only support Single-Ended
ERROR: [Drc 23-20] Rule violation (IOSTDTYPE-1) IOStandard Type - I/O port vinp_i[4] is Differential but has an IOStandard of LVCMOS33 which can only support Single-Ended[/code]
Could you give me some advice, so i could figure out the issue.
Thanks
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