v1.1 125 MHz Reference/Clock Distribution

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buhl66
Posts: 2
Joined: Thu Oct 01, 2015 4:03 am

v1.1 125 MHz Reference/Clock Distribution

Post by buhl66 » Sun Nov 08, 2015 7:14 pm

Hi,
I hope this is not a repeat, but the present instructions on the Wiki don't seem to help with 125 MHz reference distribution for v1.1.
I'm developing a high dynamic range 30 MHz - 6 GHz transceiver module I hope to release soon, and getting the 125 MHz ADC clock distibuted to external synthesis is critical.
Thanks!

Nils Roos
Posts: 1441
Joined: Sat Jun 07, 2014 12:49 pm
Location: Königswinter

Re: v1.1 125 MHz Reference/Clock Distribution

Post by Nils Roos » Mon Nov 09, 2015 12:18 am

Reference clock distribution has not been explicitly factored into the design of the Red Pitaya, by the looks of it. However, the ADC clock is driving most of the internal logic, so it is readily available to route to one of the outputs. I'm not sure if the GPIOs are suitable with regards to signal integrity, but there are also the daisy chain connectors.

lene85
Posts: 23
Joined: Tue Sep 08, 2015 3:04 pm

Re: v1.1 125 MHz Reference/Clock Distribution

Post by lene85 » Mon Nov 09, 2015 6:55 pm

Hi Buhl66,
I assume you know this page:
http://wiki.redpitaya.com/index.php?tit ... _ADC_clock

I see three possibilities for you:
1) Take the clock signal from the 125 MHz oscillator, which goes through R25 and R26 into the FPGA. Proper impedance matching might be needed here.
2) The two FPGA pins FCLK_P and FCLK_N were conceived to provide an alternative differential clock signal, which comes from inside the FPGA. In the standard scheme, one can remove R25 and R26 and instead place 0Ohm resistors at R27 and R28 to feed this clock to the ADC. However, you could as well leave everything as is and solder a wire on the FPGA-sided pads for R27 and R28 to get that clock signal out. In the standard FPGA file, the clock output is disabled. You have to recompile the bitfile in Vivado with the following modification in red_pitaya_top.v,
https://github.com/RedPitaya/RedPitaya/ ... taya_top.v

there are lines 335-337
assign adc_clk_o = 2'b10;
//ODDR i_adc_clk_p ( .Q(adc_clk_o[0]), .D1(1'b1), .D2(1'b0), .C(fclk[0]), .CE(1'b1), .R(1'b0), .S(1'b0));
//ODDR i_adc_clk_n ( .Q(adc_clk_o[1]), .D1(1'b0), .D2(1'b1), .C(fclk[0]), .CE(1'b1), .R(1'b0), .S(1'b0));

which must be changed to
//assign adc_clk_o = 2'b10;
ODDR i_adc_clk_p ( .Q(adc_clk_o[0]), .D1(1'b1), .D2(1'b0), .C(fclk[0]), .CE(1'b1), .R(1'b0), .S(1'b0));
ODDR i_adc_clk_n ( .Q(adc_clk_o[1]), .D1(1'b0), .D2(1'b1), .C(fclk[0]), .CE(1'b1), .R(1'b0), .S(1'b0));

3) Instead of 2, you can in principle output the clock signal at any clock-capable pins, for example the pair DIO3 P and N. For this you can copy-paste the code of 2, but also need the change the constraints file a little. If you need advice on that, I can help you.

A fourth possibility is to use an external clock in the first place. I have successfully used a 10 MHz reference, as is provided by most commercial measurement devices, to derive a 125 MHz clock with a PLL in the FPGA (using the MMCM module). Here as well i could post some code if you want to know more about that option.

buhl66
Posts: 2
Joined: Thu Oct 01, 2015 4:03 am

Re: v1.1 125 MHz Reference/Clock Distribution

Post by buhl66 » Wed Nov 18, 2015 7:25 am

Hi,

Thanks for the fast reply, Nils, and also for the detailed options, lene85.

My board does not look like the Wiki page - I have a v1.1. Or, I could just be very confused. The parts are also very tiny!

Definitely, distributing the base reference instead of going through any non-specialized or multiple gates (like routing through the FPGA) is generally the best for synchronous RF applications (esp. freq. synth.) I've worked with in the past. I've seen several 10's of dB improved performance in phase noise and effective accuracy in high-precision applications.

After I figure out what I'm going to do (and/or become un-confused), I'll do my best to remember to post it back here, and eventually I'll be able to report how well it worked.

Thanks!

Nils Roos
Posts: 1441
Joined: Sat Jun 07, 2014 12:49 pm
Location: Königswinter

Re: v1.1 125 MHz Reference/Clock Distribution

Post by Nils Roos » Wed Nov 18, 2015 11:11 am

My board does not look like the Wiki page - I have a v1.1. Or, I could just be very confused. The parts are also very tiny!
The location of the clock 'jumpers' has not changed between 1.0 and 1.1. The top side parts are obscured by the heat sink. On the bottom side, it is the isolated group of 2x3 solderpads roughly in the center between the expansion connectors.

circuitqed
Posts: 1
Joined: Sat Aug 01, 2015 12:57 am

Re: v1.1 125 MHz Reference/Clock Distribution

Post by circuitqed » Fri Jan 08, 2016 1:51 am

You mention that you were able to use an external 10MHz reference. I would very much like to be able to derive the fpga/ADC clock from a 10MHz reference source (i.e. http://www.thinksrs.com/products/FS725.htm) and have the clocks derived from that. You mentioned that you had some code that implemented that. I would be very grateful if you could post it if you are willing to share it.
lene85 wrote:Hi Buhl66,
I assume you know this page:
http://wiki.redpitaya.com/index.php?tit ... _ADC_clock

I see three possibilities for you:
1) Take the clock signal from the 125 MHz oscillator, which goes through R25 and R26 into the FPGA. Proper impedance matching might be needed here.
2) The two FPGA pins FCLK_P and FCLK_N were conceived to provide an alternative differential clock signal, which comes from inside the FPGA. In the standard scheme, one can remove R25 and R26 and instead place 0Ohm resistors at R27 and R28 to feed this clock to the ADC. However, you could as well leave everything as is and solder a wire on the FPGA-sided pads for R27 and R28 to get that clock signal out. In the standard FPGA file, the clock output is disabled. You have to recompile the bitfile in Vivado with the following modification in red_pitaya_top.v,
https://github.com/RedPitaya/RedPitaya/ ... taya_top.v

there are lines 335-337
assign adc_clk_o = 2'b10;
//ODDR i_adc_clk_p ( .Q(adc_clk_o[0]), .D1(1'b1), .D2(1'b0), .C(fclk[0]), .CE(1'b1), .R(1'b0), .S(1'b0));
//ODDR i_adc_clk_n ( .Q(adc_clk_o[1]), .D1(1'b0), .D2(1'b1), .C(fclk[0]), .CE(1'b1), .R(1'b0), .S(1'b0));

which must be changed to
//assign adc_clk_o = 2'b10;
ODDR i_adc_clk_p ( .Q(adc_clk_o[0]), .D1(1'b1), .D2(1'b0), .C(fclk[0]), .CE(1'b1), .R(1'b0), .S(1'b0));
ODDR i_adc_clk_n ( .Q(adc_clk_o[1]), .D1(1'b0), .D2(1'b1), .C(fclk[0]), .CE(1'b1), .R(1'b0), .S(1'b0));

3) Instead of 2, you can in principle output the clock signal at any clock-capable pins, for example the pair DIO3 P and N. For this you can copy-paste the code of 2, but also need the change the constraints file a little. If you need advice on that, I can help you.

A fourth possibility is to use an external clock in the first place. I have successfully used a 10 MHz reference, as is provided by most commercial measurement devices, to derive a 125 MHz clock with a PLL in the FPGA (using the MMCM module). Here as well i could post some code if you want to know more about that option.

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