Talking to external DSP via the RP SPI1 (slave mode) on FPGA level?

Applications, development tools, FPGA, C, WEB
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Talking to external DSP via the RP SPI1 (slave mode) on FPGA level?

Post by pyzahl » Tue May 29, 2018 5:31 am


For a novel high speed and extreme precision frequency detection I am developing...

I am looking for a way to communicate with an external DSP system (Open Source Scanning Probe Controller / GXSM Project) via the SPI bus to trigger the return of data processed by the RP's FPGA at a given time on a precise timing (kHz range).

For that I like to use the SPI in slave mode, but need to manage it in some way as fast and direct as possible (no or minimal FIFO, buffering, etc.) by my own FPGA code.

Means on receiving a particular minimal data message I need to trigger an action in a FPGA logic and when completed return a few data packages.

Right now it looks like the SPI is visible on the Zynq via Linux, but it does not seam reasonable fast enough to have a Linux program watching the SPI and managing all actions via GPIO nor this makes much sense to me in this case.

I found this AXI-Quad-SPI IP, but not sure where to connect it.

Any hints how to make this happen?

best regards

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