Using DMA IP blocks in logic_orig

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Using DMA IP blocks in logic_orig

Post by kokowang » Tue Jun 05, 2018 6:58 am

I'm new to using FPGAs, if you see any dumb mistakes in what I'm saying/asking, feel free to correct me.

It seems there are DMA IP blocks connected to AXIs, which are connected to the Processing System in the logic_orig project. Can these be used to write ADC data continuously to SDRAM?
If so, how would I access/connect the HP bus? It seems there's only connections to one GP bus inside the logic_orig project.

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