Modification Project of Pavel demin (Frequency counter-4) into realtime FIR

Discussions about active development projects
Post Reply
amin
Posts: 54
Joined: Mon Feb 06, 2017 12:31 pm

Modification Project of Pavel demin (Frequency counter-4) into realtime FIR

Post by amin » Thu Jul 12, 2018 6:04 am

Hello all,
I want to make a realtime FIR filter from Pavel demin's project (frequency counter-4).
Frequency_counter_pavel.JPG
I have tried to make a modification which i have been connected M_AXIS port of axis_red_pitaya_adc_0 to S_AXIS_PHASE of dds_compiler_0 as shown image below
ADC_pavel.JPG
modification of ADC
axis_red_pitaya_adc_0 setting:
ADC DATA WIDTH 14
AXIS TDATA WIDTH 32
signal_generator_pavel.JPG
modification of signal generator
DDS compiler setting:
system clock 125MHz
SFDR 84dB
Freq resolution 0.5 Hz

I have tried to feed input IN1 ADC with external signal generator 10kHz.
But the result of output of DAC's frequency is around 5MHz and this frequency is not changed although the external signal generator's frequency has been changed.

BR,
Amin
You do not have the required permissions to view the files attached to this post.

Post Reply
jadalnie klasyczne ekskluzywne meble wypoczynkowe do salonu ekskluzywne meble tapicerowane ekskluzywne meble do sypialni ekskluzywne meble włoskie

Who is online

Users browsing this forum: No registered users and 1 guest