RedPitaya hello world hangs up a board

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Joined: Tue Nov 19, 2019 9:09 am

RedPitaya hello world hangs up a board

Post by anba » Tue Nov 19, 2019 9:16 am

I Tested a simple "hello world" application for RedPitaya FPGA: RedPitayaHelloWorldVHDL. It takes a clock from PACKAGE_PIN U18 and U19, devides it by frequency to receive 1Hz, and outputs counter to LEDs. After making a bitstram and writing to FPGA by command:

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cat bitstram.bit > /dev/xdevcfg
LEDs blinks good, but Linux on board of RedPitaya hangsup. Why it's happening? and how to avoid it?

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Joined: Tue Nov 19, 2019 9:09 am

Re: RedPitaya hello world hangs up a board

Post by anba » Wed Nov 27, 2019 12:35 am

There is an answer on stackowerflow:
You need to instantiate a Zynq "PS7" component in your design, that is the interface between the Linux SoC part and the FPGA fabric, there is also a wizard in Vivado to configure this. If this component is not in the design then programming the bitstream crashes the SoC.

If the Linux on Red Pitaya also assumes the presence of any AXI slaves on the FPGA fabric side, omitting these from the design might also cause a lock up, but this is less likely to be the problem.
But I don't agree with it because of
David, great thank you dir your reply. Are you sure that ps7 is needed in all zyxq 7 projects? Exactly this example has no any interaction with PS7 CPU. No AXI and no other components. Only clock, from external source, frequency divider and output port for LED. FPGA fabric is self sufficient. Why PS7 is needed for not hunging?
Are Any other thoughts?

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Joined: Tue Mar 03, 2020 3:36 pm

Re: RedPitaya hello world hangs up a board

Post by pierre.hericourt » Tue Mar 10, 2020 7:47 pm

the first steps with vhdl, vivado 2019.2 and Red Pitaya are not really obvious !
I was facing the same issue and after reading Anton Potocnik verilog guide I finally got a running example just with vivado gui mode and few vhdl lines (too difficult to learn tcl and vhdl at the same time)
Here is my recipe but CARE : I'm just a beginner !

- create a new empty project, select part xc7z010clg400-1
- create a constraints file to address the led

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set_property IOSTANDARD LVCMOS33 [get_ports led_0]
set_property SLEW       SLOW     [get_ports led_0]
set_property DRIVE      4        [get_ports led_0]
set_property PACKAGE_PIN J14     [get_ports led_0]
create a vhdl source file which contains our blinking mechanic

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library IEEE;

entity blink is
  port ( 
    clk : in  std_logic;
    led : out std_logic
end blink;

architecture Behavioral of blink is
    signal state : std_logic;
    -- 100Mhz, 10ns, 1s => 10E8
    constant max_count : natural := 10000000;

    clk_p : process(clk)
        variable count : natural range 0 to max_count;
        if rising_edge(clk) then
            if count < max_count/2 then
                -- 1/2s on
                state <= '1';
                count := count + 1;
            elsif count < max_count then
                state <= '0';
                count := count + 1;
            elsif count = max_count then
                state <= '0';
                count := 0;
            end if;
        end if;
    end process clk_p; 

    led <= state;

end Behavioral;
- create a clock design (IP Integrator)
- add ZYNQ7 Processing System IP (press button +)
- connect FCLK_CLK0 to M_AXI_GP0_ACLK
- create HDL Wrapper (right click on block design source)
- add module to block design (right click on vhdl source)
- connect FCLK_CLK0 to RTL clk
- make RTL led external (right click 'make external' on led port : auto connect to our physical led described in constraints.xdc)
- generate bit stream
- scp to Red Pitaya
- cat file.bit > /dev/xdevcfg

Hope it helps
Pierre Héricourt

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