RedPitaya Open project Vivado - FPGA programming
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RedPitaya Open project Vivado - FPGA programming
Hello ,
I am a new RP programmer ,
I have a good knowledge of linux and I did basic app on the software part
but i have to understande the FPGA part (the hard )
So i had installed [Vivado + SDK] on Windows but in
1) What sources I have to download ?
2) How can I open the Verilog project on vivadeo ?
Thank for your help
I am a new RP programmer ,
I have a good knowledge of linux and I did basic app on the software part
but i have to understande the FPGA part (the hard )
So i had installed [Vivado + SDK] on Windows but in
1) What sources I have to download ?
2) How can I open the Verilog project on vivadeo ?
Thank for your help
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- Posts: 1441
- Joined: Sat Jun 07, 2014 12:49 pm
- Location: Königswinter
Re: RedPitaya Open project Vivado - FPGA programming
Hi,
I recommend you either fork / clone the RedPitaya github repository or download the contents as a zip archive. Within that, the folder "fpga" has all code that is used to build the fpga logic.
But ... with the 0.94 ecosystem release, a proper project file for the Vivado GUI is no longer included. This means you'll have to do some preparations to work with the project in Vivado. Nothing too complicated though, just do the following:
I recommend you either fork / clone the RedPitaya github repository or download the contents as a zip archive. Within that, the folder "fpga" has all code that is used to build the fpga logic.
But ... with the 0.94 ecosystem release, a proper project file for the Vivado GUI is no longer included. This means you'll have to do some preparations to work with the project in Vivado. Nothing too complicated though, just do the following:
- edit the file fpga/red_pitaya_vivado_project.tcl and change the line
into
Code: Select all
read_verilog .srcs/sources_1/bd/system/hdl/system_wrapper.v
Code: Select all
read_verilog project/redpitaya.srcs/sources_1/bd/system/hdl/system_wrapper.v
- start Vivado, at the bottom of the main screen you have the "Tcl Console"
- use the tcl console to navigate into the fpga-folder with the command "cd" (on my machine it would be "cd /Users/Nils/Documents/RedPitaya/fpga")
- execute "source red_pitaya_vivado_project.tcl" in the tcl console and watch while Vivado magically builds the project
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Re: RedPitaya Open project Vivado - FPGA programming
Hollllaaaa it's work !!! thank you very much Nils Roos !!!!
your response was clear and precise
your response was clear and precise
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Re: RedPitaya Open project Vivado - FPGA programming
Glad it got you started^^
I forgot to mention, after generating the project, you should revert the changes in fpga/red_pitaya_vivado_project.tcl or the Makefile build won't work.
There are some more points that bear emphasizing:
1. Some of the contents of the "project" folder are a copy of the sources in fpga/rtl and fpga/sdc .
As such, any changes you make to them will not affect the bitstream that is generated by the "make"-buildprocess. To get your changed code into a standard ecosystem build, you must copy the files from fpga/project/redpitaya.srcs/sources_1/imports/rtl to fpga/rtl and the constraints from fpga/project/redpitaya.srcs/constrs_1/imports/sdc to fpga/sdc .
If you made changes to the blockdesign, it gets more complicated: you will need to recreate the changes in the form of tcl statements for the script fpga/ip/system_bd.tcl .
2. The generated project is great for having a look around and discover how everything works. But it is missing some settings that are important to successfully build a bitstream from within the Vivado GUI. Take a look at the sections "# run synthesis" and following in fpga/red_pitaya_vivado.tcl to see what settings are used.
The generated project also does not have the simulation and testbench sources, you must import them separately if you want to use them.
I forgot to mention, after generating the project, you should revert the changes in fpga/red_pitaya_vivado_project.tcl or the Makefile build won't work.
There are some more points that bear emphasizing:
1. Some of the contents of the "project" folder are a copy of the sources in fpga/rtl and fpga/sdc .
As such, any changes you make to them will not affect the bitstream that is generated by the "make"-buildprocess. To get your changed code into a standard ecosystem build, you must copy the files from fpga/project/redpitaya.srcs/sources_1/imports/rtl to fpga/rtl and the constraints from fpga/project/redpitaya.srcs/constrs_1/imports/sdc to fpga/sdc .
If you made changes to the blockdesign, it gets more complicated: you will need to recreate the changes in the form of tcl statements for the script fpga/ip/system_bd.tcl .
2. The generated project is great for having a look around and discover how everything works. But it is missing some settings that are important to successfully build a bitstream from within the Vivado GUI. Take a look at the sections "# run synthesis" and following in fpga/red_pitaya_vivado.tcl to see what settings are used.
The generated project also does not have the simulation and testbench sources, you must import them separately if you want to use them.
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Re: RedPitaya Open project Vivado - FPGA programming
thanks again !!! those tips are saving me a lot of time ^^ !!
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Re: RedPitaya Open project Vivado - FPGA programming
Hi Nils, There is a file called FPGA map address in /redpitaya/fpga/doc.What confused is, we konw if want to address logic and the logic must be customed as AXI ip, but in redpitaya.xpr opened by vivado, I did not see any other ip in the project?
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Re: RedPitaya Open project Vivado - FPGA programming
In Vivado, open the block design "system.bd" - just click "Open Block Design" and it will open, since it's the only one in the project. There are a couple of AXI busses in that design, one is connected to the XADC IP and 3 of them (M_AXI_GP0, S_AXI_HP0/1) terminate in connections to the fpga processing logic.
When the block design is open, you also have the Address Editor tab, where you can see the assigned ranges.
The detailed list, which you found in the doc/ folder is just a summary of the different decoders that further compartmentalize the address ranges - you can find the correspondig logic in red_pitaya_hk.v, red_pitaya_scope.v, etc - usually towards the end of the code.
When the block design is open, you also have the Address Editor tab, where you can see the assigned ranges.
The detailed list, which you found in the doc/ folder is just a summary of the different decoders that further compartmentalize the address ranges - you can find the correspondig logic in red_pitaya_hk.v, red_pitaya_scope.v, etc - usually towards the end of the code.
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Re: RedPitaya Open project Vivado - FPGA programming
In RedPitaya_HDL_memory_map, the Arbitrary signal generator's address range is 0x40200000~0x402FFFFF. But why I didn't see the Arbitrary signal generator's address range in address editor of vivado?
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Duplicate of this question - see there for the continuation.
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Duplicate of this question - see there for the continuation.
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Re: RedPitaya Open project Vivado - FPGA programming
Hi Nils,
I am trying to get started creating custom FPGA code on the Red Pitaya. Let's say I added a simple adder to the block design that is connected to my PS. I grabbed the appropriate TCL commands and added them to system_bd.tcl. I copied the files from "fpga/project/redpitaya.srcs/sources_1/imports/rtl" to "fpga/rtl", and I did the same for the constraint files. I work my way through the build process. Once I have successfully build everything in the "fpga" directory, how do I move those changes onto the Red Pitaya? Do I need to rebuild everything in the root repository folder as well, or is building just the stuff in the "fpga" folder sufficient? Additionally, how do I know the address to mmap to access the AXI registers that the adder is connected to?
Thank you for your help; I know this is a long question.
Jon
I am trying to get started creating custom FPGA code on the Red Pitaya. Let's say I added a simple adder to the block design that is connected to my PS. I grabbed the appropriate TCL commands and added them to system_bd.tcl. I copied the files from "fpga/project/redpitaya.srcs/sources_1/imports/rtl" to "fpga/rtl", and I did the same for the constraint files. I work my way through the build process. Once I have successfully build everything in the "fpga" directory, how do I move those changes onto the Red Pitaya? Do I need to rebuild everything in the root repository folder as well, or is building just the stuff in the "fpga" folder sufficient? Additionally, how do I know the address to mmap to access the AXI registers that the adder is connected to?
Thank you for your help; I know this is a long question.
Jon
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Re: RedPitaya Open project Vivado - FPGA programming
You copy fpga/out/red_pitaya.bit to the Red Pitaya and do "cat red_pitaya.bit >/dev/xdevcfg" in a console. This immediately activates your new logic until the next reboot.how do I move those changes onto the Red Pitaya?
If you want to have your modified logic load on boot, you will need to make the target "tmp/boot.bin" from the root folder and replace the existing boot.bin with your new one.
You don't "know", you "tell". In fpga/ip/system_bd.tcl there are a couple of lines with "create_bd_addr_seg". Add one for your new AXI device at a free address range of your choosing.how do I know the address to mmap to access the AXI registers that the adder is connected to?
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