Output clock constraints

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Output clock constraints

Post by fbalakirev » Tue Apr 23, 2024 4:57 pm

We are exploring the options for exporting the ADC clock from one Red Pitaya to the Ext. clck. +/- input pins of another Red Pitaya, that is pins 23-24 on E2 connector.

There's an old forum thread that touched upon this question - viewtopic.php?t=1012

One suggestion there is to drive clock-capable pair of pins, e.g. DIO3 P and N with the 125 MHz clock signal, but it does not mention the proper constraints.

There's a couple of clock output examples in the official github, e.g adc_clk_o is configured with LVCMOS18 single-ended standard and is driven with a pair of ODDR primitives. On the other hand, dasy_o clock is configured with DIFF_HSTL_I_18 standard and is driven with a OBUFDS primitive respectably.

Do you happen to have any recommendations?

We also tested the new click shield, which works fine as a clock source, but presented some issues with asynchronous triggering, so we are exploring the alternatives.

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